Semiconductor devices are continuously improved to enhance device performance. For example, a transistor device includes a gate stack on a semiconductor substrate. The gate stack includes a gate electrode over a gate dielectric layer. Smaller devices and shrinking ground rules are the keys to enhance performance and to reduce cost. As devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next.
In standard CMOS devices, polycrystalline silicon (poly-Si) is the standard gate material used. The technology of fabricating CMOS devices using poly-Si gates has been in a constant state of development, and poly-Si gates are widely used in the semiconductor industry. However, there are problems associated with using a poly-Si gate. For example, due to the poly depletion effect and relatively high electrical sheet resistance, poly-Si gates commonly used in CMOS devices are becoming a stymieing factor in chip performance for devices of submicron generations. Another problem with poly-Si gates is that the dopants in the poly-Si gate, such as boron, can easily diffuse through the gate dielectric causing further degradation of the device performance.
There is a great difficulty in maintaining performance improvements in devices of submicron generations. Therefore, methods for improving performance without scaling down have become of interest. There is a promising avenue toward higher gate dielectric capacitance without having to make the gate dielectric actually thinner. This approach involves the use of high-K materials. The dielectric constant of such materials is significantly higher than that of silicon dioxide (SiO2). A high-K material may be significantly thicker than SiO2, and still have a lower equivalent oxide thickness (EOT) value. The EOT, as known in the art, refers to the thickness of such a SiO2 layer which has the same capacitance per unit area as the dielectric layer in question. However, there are problems associated with using such high-K material. For example, any oxygen that diffuses to high-k material causes unwanted dielectric growth. This is undesirable, as the resulting thickness variations can result in the overall geometry and uniformity of the devices being significantly impaired. Moreover, the increased gate dielectric thickness degrades drain currents and also limits gate length scaling.